1. Technical Field
The present invention relates generally to semiconductor technology, and more specifically to semiconductor-on-insulator constructions that control floating body effects.
2. Background Art
At the present time, electronic products are used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are used in everything from airplanes and televisions to wristwatches.
Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each wafer worth hundreds or thousands of dollars.
Integrated circuits are made up of hundreds to millions of individual components. One common component is the semiconductor transistor. The most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon-based semiconductor device is a complementary metal oxide semiconductor (“CMOS”) transistor.
The principal elements of a CMOS transistor generally consist of a silicon substrate having shallow trench oxide isolation regions cordoning off transistor areas. The transistor areas contain polysilicon gates on silicon oxide gates, or gate oxides, over the silicon substrate. The silicon substrate on both sides of the polysilicon gate is slightly doped to become conductive. These lightly doped regions of the silicon substrate are referred to as “shallow source/drain junctions”, which are separated by a channel region beneath the polysilicon gate. A curved silicon oxide or silicon nitride spacer, referred to as a “sidewall spacer”, on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain (“S/D”) junctions, which are called “deep S/D junctions”.
To complete the transistor, a silicon oxide dielectric layer is deposited to cover the polysilicon gate, the curved spacer, and the silicon substrate. To provide electrical connections for the transistor, openings are etched in the silicon oxide dielectric layer to the polysilicon gate and the S/D junctions. The openings are filled with metal to form electrical contacts. To complete the integrated circuits, the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
In operation, an input signal to the gate contact to the polysilicon gate controls the flow of electric current from one S/D contact through one S/D junction through the channel to the other S/D junction and to the other S/D contact.
Transistors are fabricated by thermally growing a gate oxide layer on the silicon substrate of a semiconductor wafer and forming a polysilicon layer over the gate oxide layer. The oxide layer and polysilicon layer are patterned and etched to form the gate oxides and polysilicon gates, respectively. The gate oxides and polysilicon gates in turn are used as masks to form the shallow S/D regions by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate. The ion implantation is followed by a high-temperature anneal above 700° C. to activate the implanted impurity atoms to form the shallow S/D junctions.
A silicon nitride layer is deposited and etched to form sidewall spacers around the side surfaces of the gate oxides and polysilicon gates. The sidewall spacers, the gate oxides, and the polysilicon gates are used as masks for the conventional S/D regions by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate into and through the shallow S/D junctions. The ion implantation is again followed by a high-temperature anneal above 700° C. to activate the implanted impurity atoms to form the S/D junctions.
After formation of the transistors, a silicon oxide dielectric layer is deposited over the transistors and contact openings are etched down to the S/D junctions and to the polysilicon gates. The contact openings are then filled with a conductive metal and interconnected by formation of conductive wires in other interlayer dielectric (“ILD”) layers.
As transistors and integrated circuit dimensions have decreased in size and increased in operating speeds, specialized fabrication architectures and technologies have evolved to enable these capabilities. One such technology, called semiconductor-on-insulator (“SOI”), has a base semiconductor substrate layer (such as silicon); a buried insulating layer (such as silicon oxide) over the semiconductor substrate layer; and an upper semiconductor region over the buried insulating layer. Circuitry is then formed in the upper semiconductor region.
An SOI device formed on such an SOI substrate is then completely isolated by the buried oxide layer. This reduces junction capacitance, achieves low power consumption, and enables very high speed operation. For example, metal oxide semiconductor field effect transistors (“MOSFETs”) are well known in the field of semiconductors. SOI MOSFETs have been demonstrated to be superior to bulk silicon MOSFETs in low-power, high-speed, very large scale integration (“VLSI”) applications.
SOI devices have often been dubbed as the successor to the reigning bulk silicon CMOS field effect transistor (“FET”) devices. SOI device advantages include excellent device isolation (protecting against cross talk), almost null leakage, latch-up immunity, dynamic coupling, reduced short-channel effects, improved radiation hardness, lower parasitic junction capacitance (enabling higher circuit speed), reduced junction leakage currents, lower power consumption, and simplified device isolation and fabrication.
Attention is thus now focused on SOI metal oxide semiconductor (“MOS”) transistors as high-speed, low-power devices. However, one problem with forming FETs on an SOI wafer is the floating body effect (“FBE”). The FBE occurs because the buried oxide layer isolates the channel, or body, of the transistor from the fixed electrical potential of the silicon substrate. The transistor body therefore takes on a charge based on recent operation of the transistor.
Since the body of a conventional SOI MOS transistor is in an electrically floating state, a parasitic bipolar effect is produced. This causes the charge carriers (holes in nMOSFETs and electrons in pMOSFETs) that are regularly generated during circuit operation to accumulate near the source/body junctions of the MOSFET. Eventually, sufficient carriers will accumulate to electrically forward bias the transistor body with respect to the source. The FBE then causes the current-to-voltage curve for the transistor to distort or kink, which in turn causes the threshold voltage for operating the transistor to fluctuate.
A threshold voltage that is lowered by this effect causes extra current to start flowing, resulting in a “kink” in the transistor's electrical characteristics. In analog circuits, the extra current flow reduces the achievable gain and dynamic swing. In digital circuits, the extra current flow gives rise to an abnormality in the transfer characteristics. Additionally, the FBE causes higher device leakages, undesirable transient effects, and can cause circuit instability and device malfunction.
One attempted solution for the FBE is to provide a contact to the transistor body to collect and remove the hole current. However, currently available hole collection schemes, including the use of a side contact or a mosaic source, are inefficient and consume significant amounts of wafer area. Complex transistor designs are therefore often required to reduce the FBE. For example, substrate contact schemes, such as a low barrier body contact (“LBBC”), have been utilized to provide a contact for current collection for the SOI substrate, thereby reducing the FBE. However, providing substrate contacts on an SOI substrate requires space and can add process complications.
Accordingly, there is a strong continuing need for a semiconductor circuit structure, and a method for forming such a structure, that includes the low junction capacitance and low “off” state leakage characteristics of SOI FET based circuits, but does not suffer the disadvantages of a floating body potential. In particular, there exists a strong need for an uncomplicated and inexpensive SOI structure that can remove extra carriers, such as by promoting carrier recombination, thereby removing charges from the channel and reducing the floating body effect.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.